Electro-optical device, process for manufacturing the same, and electronic apparatus

ABSTRACT

An electro-optical device includes above a substrate: data lines extending in a first direction; scanning lines extending in a second direction in such a manner that the scanning lines and data lines cross each other; pixel electrodes and thin-film transistors each placed in corresponding regions corresponding to intersections of the scanning lines and data lines; storage capacitors disposed below the data lines and each electrically connected to the corresponding thin-film transistors and pixel electrodes; a capacitor line disposed above the data lines; first junction electrodes, formed using the same film used to form the data lines, each electrically connecting the corresponding pixel potential capacitor electrodes of the storage capacitors and pixel electrodes; and second junction electrodes, formed using the same film as that to form the data lines, each electrically connecting the corresponding constant potential capacitor electrodes of the storage capacitors and the capacitor line. The data lines, first junction electrodes, and second junction electrodes each including a nitride film.

BACKGROUND OF THE INVENTION

[0001] 1. Field of Invention

[0002] The present invention relates to an electro-optical device, suchas a liquid crystal device and an electronic apparatus including such anelectro-optical device. The present invention also relates to anelectroluminescent (EL) device, a device including an electron-emittingelement, and an electrophoretic device, such as an electronic papersheet, wherein the electron-emitting element-including device includesfield emission displays and surface-conduction electron-emitterdisplays.

[0003] 2. Description of Related Art

[0004] Electro-optical devices, such as liquid crystal devices, eachincluding the following components have been known: a pair of substratesand electro-optical materials, such as liquid crystals, placedtherebetween. In such electro-optical devices, an image can be displayedby allowing light to pass through the substrates and electro-opticalmaterials. The display of an image can be achieved as follows: thetransmittance of light is varied for each pixel by changing the state ofsuch electro-optical materials, thereby displaying different shades ofgray for each pixel in a recognizable manner.

[0005] As such electro-optical devices, an active matrix addressingelectro-optical device having on one of a pair of the substrates, pixelelectrodes arranged in a matrix, scanning and data lines extendingbetween the pixel electrodes, and thin-film transistors (TFTs)functioning as pixel-switching elements is known. In the active matrixaddressing electro-optical device, each TFT is placed between each pixelelectrode and data line for controlling the conduction therebetween. TheTFTs are electrically connected to the corresponding scanning lines anddata lines. Thereby, the TFTs can be turned on or off using the scanninglines and when the TFTs are turned on, image signals transmitted fromthe data lines can be applied to the pixel electrodes, that is, thelight transmittance can be varied for each pixel.

[0006] In the electro-optical devices described above, the abovecomponents are arranged on one of the substrates. In order to arrangethe components in a two-dimensional manner, a large area is necessary,and therefore there is a problem in that a pixel aperture ratio islowered, wherein the pixel aperture ratio is defined as the ratio of thearea of regions through which light passes to the entire surface area ofthe substrate. Thus, in related art manufacturing processes, thefollowing configuration has been employed: the components are arrangedin a three-dimensional manner, that is, the components are stacked byusing interlayer insulating layers. In particular, the TFTs and thescanning lines functioning as gate electrodes of the TFTs are placed onone of the substrates, the data lines are placed thereabove, and thepixel electrodes and the like are placed thereabove. According to thisconfiguration, the devices can be miniaturized and the pixel apertureratio can be increased by arranging the components in an appropriatemanner.

[0007] However, in the related art electro-optical devices, there is aproblem that the life of the TFTs is relatively short. This is becausewhen a semiconductor layer or gate insulating layer, which is acomponent of each TFT, absorbs moisture, water molecules diffuse intothe interface between the semiconductor layer and gate insulating layer,whereby positive charges are generated and therefore the thresholdvoltage V_(th) is increased in a relatively short period. Thisphenomenon is apt to occur in p-channel TFTs. The short life of the TFTsnaturally affects the electro-optical devices as a whole so that theimage quality is deteriorated from a relatively early period, and thereis a fear that the devices do not operate.

SUMMARY OF THE INVENTION

[0008] The present invention has been made to address the above problem,provides an electro-optical device that includes long-life TFTs and candisplay a high-quality image. Furthermore, the present inventionprovides an electronic apparatus including such an electro-opticaldevice.

[0009] In order to address the above problem, an electro-optical deviceof the present invention includes above a substrate: data linesextending in a first direction; scanning lines extending in a seconddirection in such a manner that the scanning lines and data lines crosseach other; pixel electrodes and thin-film transistors each placed inthe regions corresponding to the intersections of the scanning lines anddata lines; storage capacitors disposed below the data lines and eachelectrically connected to the corresponding thin-film transistors andpixel electrodes; a capacitor line disposed above the data lines; firstjunction electrodes, formed using the same film as that to form the datalines, to each electrically connect the corresponding pixel potentialcapacitor electrodes and pixel electrodes; and second junctionelectrodes, formed using the same film as that to form the data lines,to each electrically connect the corresponding constant potentialcapacitor electrodes and the capacitor line. The data lines, firstjunction electrodes, and second junction electrodes each include anitride film.

[0010] Since this electro-optical device includes the scanning lines,data lines, pixel electrodes, and thin-film transistors, active matrixaddressing can be realized. Furthermore, since the above-mentionedcomponents form part of a layered structure, the electro-optical devicecan be compact. Furthermore, the pixel aperture ratio can be enhanced byarranging the above components in an appropriate manner.

[0011] In particular, since the data lines, first junction electrodes,and second junction electrodes each include a nitride film, which caneffectively reduce or prevent the penetration or diffusion of moisture,moisture can be reduced or prevented from entering the semiconductorlayers of the thin-film transistors. Thereby, the problem that thresholdvoltage of the thin-film transistors is raised can be greatly reduced orprevented from occurring; hence, the life of the electro-optical devicecan be enhanced.

[0012] In an aspect of the electro-optical device of the presentinvention, the data lines, first junction electrodes, and secondjunction electrodes each preferably include a nitride film on aconductive layer disposed. In particular, the data lines, first junctionelectrodes, and second junction electrodes preferably have laminatedlayer structure including an aluminum film, titanium nitride film, andsilicon nitride film.

[0013] According to this configuration, the data lines contain aluminum,which has relatively low resistance; hence, image signals can becontinuously transmitted to the thin-film transistors and pixelelectrodes. Furthermore, the data lines each include a silicon nitridefilm, which is relatively excellent in reducing or preventing moisturepenetration; hence, the thin-film transistors are allowed to have anenhanced moisture resistance and therefore have a long life. The siliconnitride films may be formed by a plasma CVD process.

[0014] The titanium nitride films in the first and second junctionelectrodes function as barrier metal films to prevent the first andsecond junction electrodes from being penetrated when contact holes areformed in those electrodes by an etching process. Furthermore, the firstand second junction electrodes, as well as the data lines, blockmoisture penetration; hence, the thin-film transistors are allowed tohave an enhanced moisture resistance and therefore have a long life.

[0015] In an aspect of the electro-optical device of the invention,third junction electrodes are formed using the same film as that used toform the capacitor line, and the first junction electrodes are eachelectrically connected to the corresponding pixel electrodes with thecorresponding third junction electrodes. The capacitor line and thirdjunction electrodes each include a nitride film on a conductive film.Furthermore, the capacitor line and third junction electrodes preferablyhave laminated layer structure including an aluminum film, titaniumnitride film, and silicon nitride film.

[0016] According to this configuration, the capacitor line locatedbetween the data lines and pixel electrodes can reduce or preventcapacitor coupling from occurring therebetween. That is, a possibilitythat voltage fluctuation occurs in the pixel electrodes upon conductionof the data lines can be reduced, thereby displaying a high-qualityimage.

[0017] In an aspect of the electro-optical device of the invention,fourth junction electrodes are formed on the same insulating layerhaving the fourth junction electrodes and thin-film transistors thereon,and the pixel potential capacitor electrodes are each electricallyconnected to the corresponding first junction electrodes with thecorresponding fourth junction electrodes.

[0018] According to this configuration, the pixel potential capacitorelectrodes are each electrically connected to the corresponding pixelelectrodes with electrodes disposed below the pixel potential capacitorelectrodes, and therefore penetration can be reduced or prevented fromoccurring when the storage capacitors are formed by an etching process.

[0019] In another aspect of the electro-optical device, the fourthjunction electrodes are formed using the same film used to form gateelectrodes of the thin-film transistors.

[0020] According to this configuration, the fourth junction electrodescan be obtained in a more simple way and at lower cost as compared withanother configuration in which the fourth junction electrodes are formedin special steps. Furthermore, when the scanning lines include the gateelectrodes, at least the gate electrodes of the scanning lines arepreferably formed of a conductive polysilicon film so as to functioneffectively. In this case, the fourth junction electrodes also includethe conductive polysilicon film and the like.

[0021] As is clear from this aspect of the present invention, the“fourth junction electrodes” of the invention need not be formed usingthe same film used to form the gate electrodes. In this case, the fourthjunction electrodes and the gate electrodes are not made of the samematerial, and therefore a material used to form the fourth junctionelectrodes may be freely selected as long as the material is conductive.

[0022] In this configuration, the scanning lines and gate electrode areplaced in different levels of the layered structure.

[0023] According to this configuration, the scanning lines may be placedon a lower level of the layered structure and the gate electrodes may beplaced on an upper level thereof. The converse is also possible. As aresult, in a level including the gate electrodes, in contrast to thecase of forming the scanning lines, a striped pattern need not beformed. When the thin-film transistors are arranged in a matrix, adotted pattern corresponding to such a matrix may be formed, therebyobtaining the gate electrodes. That is, the level including the gateelectrodes can have a relatively large redundant area.

[0024] Thus, when the gate electrodes are formed using the same filmused to form the fourth junction electrodes as described above, there isan advantage in that the fourth junction electrodes can be readilyformed.

[0025] In this aspect, the scanning lines preferably have protrusionsextending in parallel to the first direction.

[0026] According to this configuration, since the scanning lines areplaced on a level different from a level than the gate electrodes or thethin-film transistor including the gate electrodes. The scanning lineshave the protrusions extending in parallel to the first direction. Thescanning lines can function as a lower light-shielding layer to shieldthe thin-film transistors against light. That is, light is reduced orprevented from entering semiconductor layers of the thin-filmtransistors, thereby reducing or preventing photo-leakage current frombeing generated. Thus, a high-quality image with no flicker can bedisplayed.

[0027] In this configuration, the scanning lines are preferably formedof conductive polysilicon or tungsten silicide (WSi), which hasrelatively satisfactory light-absorbing properties.

[0028] In another aspect of the electro-optical device of the presentinvention, the storage capacitors may each further include correspondingdielectric layers each disposed between the corresponding pixelpotential capacitor electrodes and constant potential capacitorelectrodes. The dielectric layers preferably include a plurality ofsub-layers of different materials. One of the sub-layers preferably isformed of a material having a dielectric constant larger than those ofother materials of other sub-layers. Furthermore, the dielectric layerseach preferably include corresponding silicon dioxide sub-layers andsilicon nitride sub-layers.

[0029] According to this configuration, the storage capacitors can havesuperior charge-storing properties, and therefore can further enhancepotential-maintaining properties of the pixel electrodes; hence, ahigh-quality image can be displayed. The “high dielectric constantmaterial” specified herein includes an insulating material containing atleast one selected from the group including tantalum oxide (TaOx),barium strontium titanate (BST), lead zirconate titanate (PZT), titaniumoxide (TiO₂), zirconium oxide (ZrO₂), hafnium oxide (HfO₂), siliconoxynitride (SiON), and silicon nitride (SiN). Especially when the highdielectric constant material, such as TaOx, BST, PZT, TiO₂, ZiO₂, orHfO₂ is used, capacitors having high capacitance can be formed in alimited area on the substrate. Alternatively, when the high dielectricconstant material containing silicon, such as SiO₂, SiON, or SiN isused, stress to be generated in interlayer insulating layers or the likecan be reduced.

[0030] Furthermore, according to an aspect of the invention, the pixelelectrodes and the pixel potential capacitor electrodes included in thestorage capacitors are electrically connected to each other in thelayered structure with junction electrodes disposed below the respectiveelectrodes. Namely, the pixel potential capacitor electrodes are locatedabove the junction electrodes and the pixel electrodes are also locatedabove the junction electrodes. That is, the junction electrodes arelocated at the lowest level among those of three electrodes. In thisconfiguration, since the pixel electrodes and the pixel potentialcapacitor electrodes are electrically connected to each other with thejunction electrodes, it becomes possible that electrical contacts aredisposed below the pixel electrodes and the pixel potential capacitorelectrodes, but are not disposed thereabove.

[0031] Here, that such electrical contacts are not located above thepixel potential capacitor electrodes means that the followingarrangement is not necessary to electrically connect the pixel potentialcapacitor electrodes to the pixel electrodes in contrast to related artarrangements. The pixel potential capacitor electrodes are arranged suchthat the pixel potential capacitor electrodes can be seen when thelayered structure is viewed from above. For example, when the pixelpotential capacitor electrodes are located below the constant potentialcapacitor electrodes, and if the pixel potential capacitor electrodesmust be formed by an etching process so as to be arranged in such apattern that the pixel potential capacitor electrodes can be seen fromabove, the constant potential capacitor electrodes, located above thepixel potential capacitor electrodes, must be etched to have apredetermined pattern. That is, the constant potential capacitorelectrodes must be formed by an etching process, such that the constantpotential capacitor electrodes have an area smaller than that of thepixel potential capacitor electrodes, or such that the constantpotential capacitor electrodes extend outside the pixel potentialcapacitor electrodes.

[0032] However, it is difficult to form such a pattern because the pixelpotential capacitor electrodes are penetrated in many cases duringetching. In general, conditions to form the constant potential capacitorelectrodes by an etching process must be selected such that the etchingrate of the dielectric layers is smaller than that of the constantpotential capacitor electrodes. However, in general, the dielectriclayers have a small thickness, and particularly in an aspect of thepresent invention, the dielectric layers contain the high dielectricconstant material, such as SiN or TaOx in particular, perforations mightnot be prevented from extending through the dielectric layers.Furthermore, depending on a material contained in the dielectric layers,conditions cannot be selected such that the etching rate of thedielectric layers is smaller than that of the constant potentialcapacitor electrodes. Therefore, perforations extending through thepixel potential capacitor electrodes are caused in many cases. Such aphenomenon causes, in a bad case, a short circuit between a pair ofelectrodes included in each storage capacitor, and as a result, suchstorage capacitor cannot operate any more.

[0033] In contrast, in an aspect of the present invention, the electriccontacts are located below the pixel potential capacitor electrodes.Therefore, it is not necessary to arrange the constant potentialcapacitor electrodes in such a difficult pattern.

[0034] As described above, according to an aspect of the presentinvention, the pixel potential capacitor electrodes can be securelyelectrically connected to the pixel electrodes. Furthermore, defects,such as the above-mentioned perforations caused in the pixel potentialcapacitor electrodes, the above short circuit, and the like can bereduced as well. Thus, the electro-optical device having highperformance can be provided. Furthermore, since the electro-opticaldevice including the junction electrodes and storage capacitors arrangedas described above have optimum layered structure, the electro-opticaldevice can be further miniaturized with ease and are allowed to havehigher definition.

[0035] In the electro-optical device of an aspect of the presentinvention, the capacitor line is preferably formed of a light shieldingfilm and to extend along the corresponding data lines and have a widthlarger than that of the data lines.

[0036] The electro-optical device preferably further includes a firstinsulating layer disposed as a base of the pixel electrodes and a secondinsulating layer disposed as a base of the capacitor line, wherein atleast the first insulating layer is preferably planarized.

[0037] According to this configuration, the interlayer insulating layeris disposed under the pixel electrodes and the surface thereof isplanarized by, for example, a chemical mechanical polishing (CMP)process. Therefore, the possibility that the orientation ofelectro-optical materials, such as liquid crystals is disturbed can bereduced, and thereby displaying a high-quality image becomes possible.The interlayer insulating layer disposed under the pixel electrodes hasserious irregularities, thereon, due to the junction electrodes in somecases. Therefore, the planarization of the interlayer insulating layeris advantageous to provide an electro-optical device that operates morecorrectly.

[0038] In the aspect of the electro-optical device including thecapacitor line as described above, another interlayer insulating layeris further provided as the base of the capacitor line and the surfacethereof is preferably planarized.

[0039] According to this configuration, since the additional interlayerinsulating layer is disposed as the base of the capacitor line and thesurface thereof is planarized by, for example, a CMP process, thepossibility that the orientation of electro-optical materials, such asliquid crystals, is disturbed can be reduced, and thereby displaying ahigh-quality image becomes possible.

[0040] Furthermore, in this configuration, when the interlayerinsulating layer disposed under the pixel electrodes is also planarized,the above advantage can be enhanced.

[0041] Alternatively, the electro-optical device including the capacitorline may have the following configuration: on the substrate, thescanning lines including the gate electrodes for the thin-filmtransistors are placed, the storage capacitors are placed above thescanning lines, the data lines are placed above the storage capacitors,the capacitor lines are placed above the data lines, and the pixelelectrodes are placed above the capacitor lines, wherein the storagecapacitors each include the corresponding pixel potential capacitorelectrodes, dielectric layers, and constant potential capacitorelectrodes each disposed in this order from the lower layer side, andthe junction electrodes are formed using the same film used to form thegate electrodes.

[0042] According to this configuration, the above layered structuredisposed on the substrate has an optimum arrangement, or layout.

[0043] In order to further address the above problem, a process tomanufacture an electro-optical device according to an aspect of thepresent invention includes the steps of forming, above a substrate:thin-film transistors; a first interlayer insulating layer on gateelectrodes of the thin-film transistors; storage capacitors on the firstinterlayer insulating layer, the storage capacitors being each equippedwith a pixel potential capacitor electrode, dielectric layer, andconstant potential capacitor electrode disposed in this order from thebottom; a second interlayer insulating layer on the storage capacitors;data lines, first junction electrodes, and second junction electrodes onthe second interlayer insulating layer using a conductive materialcontaining a nitride film, the data lines being each electricallyconnected to the corresponding semiconductor layers, the first junctionelectrodes being each electrically connected to the corresponding pixelpotential capacitor electrodes, and the second junction electrodes beingeach electrically connected to the corresponding constant potentialcapacitor electrodes; a third interlayer insulating layer on the datalines, first junction electrodes, and second junction electrodes; thirdjunction electrodes and a capacitor line on the third interlayerinsulating layer, the third junction electrodes being each electricallyconnected to the corresponding first junction electrodes, and thecapacitor line being electrically connected to the corresponding secondjunction electrodes; a fourth interlayer insulating layer on the thirdjunction electrodes and capacitor line; and pixel electrodes, eachelectrically connected to the corresponding third junction electrodes,on the fourth interlayer insulating layer.

[0044] According to this process, the electro-optical device can berelatively easily manufactured.

[0045] In an aspect of the manufacturing process of the invention, thestep of forming the storage capacitor includes a sub-step of forming afirst precursor film to form the pixel potential capacitor electrodes; asub-step of forming a second precursor film to form the dielectriclayers on the first precursor film; a sub-step of forming a thirdprecursor film to form the constant potential capacitor electrodes onthe second precursor film; and a sub-step of etching the first, second,and third precursor films in one step to form the pixel potentialcapacitor electrodes, dielectric layers, and constant potentialcapacitor electrodes.

[0046] According to the above aspect of the manufacturing process, inthe step of forming the storage capacitors, the first, second, and thirdprecursor films to form the pixel potential capacitor electrodes,dielectric layers, and constant potential capacitor electrodes,respectively, are once formed and these precursor films are then etchedin one step. Therefore, the three components of the storage capacitorsgenerally have the same shape when viewed from above. This makes itpossible to form the storage capacitors having a relatively largecapacitance without unnecessarily increasing the two-dimensional spacefor the components, that is, without lowering the pixel aperture ratio.Furthermore, in the above aspect, unlike in the related art, thefollowing difficult procedure is not necessary: only the constantpotential capacitor electrodes are etched but the dielectric layers andpixel potential capacitor electrodes are not etched and are allowed toremain as they are. Thus, according to an aspect of the presentinvention, the storage capacitors can be formed easily and reliably.

[0047] In another aspect of the manufacturing process of the invention,the step of forming the storage capacitors includes a sub-step offorming a first precursor film to form the pixel potential capacitorelectrodes; a sub-step of etching the first precursor film to form thepixel potential capacitor electrodes; a sub-step of forming a secondprecursor film to form the dielectric layers on the first precursorfilm; a sub-step of forming a third precursor film to form the constantpotential capacitor electrodes on the second precursor film; and asub-step of etching the third precursor film to form the dielectriclayers and constant potential capacitor electrodes, wherein the constantpotential capacitor electrodes and dielectric layers have an area largerthan that of the dielectric layers and pixel potential capacitorelectrodes.

[0048] In this aspect, unlike the former description, the firstprecursor film is etched once, whereby the pixel potential capacitorelectrodes are formed, and the dielectric layers and constant potentialcapacitor electrodes are then formed. Furthermore, in this aspect, theconstant potential capacitor electrodes have an area larger than that ofthe dielectric layers and pixel potential capacitor electrodes.Therefore, the storage capacitors having the following configuration canbe formed: a configuration in which the dielectric layers and constantpotential capacitor electrodes each cover the corresponding pixelpotential capacitor electrodes. Thus, each dielectric layer is incontact with each pixel potential capacitor electrode and constantpotential capacitor electrode with a larger area, and therefore thestorage capacitors having a larger capacitance are achieved. Morespecifically, for example, sides of these three components of thestorage capacitors can be used as capacitor portions, and as a result,increase in capacitance can be expected. Thus, when the pixel potentialcapacitor electrodes are formed to have a large thickness or the like,sides of the pixel potential capacitor electrodes have a larger area,thereby effectively obtaining an increased capacitance. In addition,according to this configuration, each pixel potential capacitorelectrode and constant potential capacitor electrode are hardlyshort-circuited.

[0049] Incidentally, in this aspect, when the third precursor film isetched, the second precursor film may be also etched.

[0050] An electronic apparatus of an aspect of the present inventionincludes the above-mentioned electro-optical device. The electronicapparatus may include a modified electro-optical device.

[0051] Since the electronic apparatus of an aspect of the inventionincludes the above-mentioned electro-optical device, the pixelelectrodes can be securely electrically connected to the storagecapacitors, which operate correctly. Thereby, a high-quality image canbe displayed. Furthermore, the following various electronic apparatusesincluding the electro-optical device, such as a liquid crystal device,having high reliability can be achieved: projective display units,liquid crystal TVs, mobile phones, electronic notebooks, wordprocessors, view finder-type or direct monitoring type video taperecorders, work stations, TV phones, POS terminals, and touch panels.

[0052] The above advantages and gains of the present invention willbecome apparent from the following description of preferred exemplaryembodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

[0053]FIG. 1 is a schematic showing an equivalent circuit includingvarious elements, wiring lines, and the like for pixels arranged, in amatrix, in an image display region of an electro-optical deviceaccording to an exemplary embodiment of the present invention;

[0054]FIG. 2 is a plan view showing a plurality of the pixels, adjacentto each other, placed on a TFT array substrate, included in theelectro-optical device according to an exemplary embodiment of thepresent invention, having data lines, scanning lines, and pixelelectrodes thereon;

[0055]FIG. 3 is a plan view showing a principal portion of FIG. 2;

[0056]FIG. 4 is a sectional view taken along the plane A-A′ of FIG. 2;

[0057]FIG. 5 is a fragmentary sectional view showing a configuration tobe compared with that shown in FIG. 4;

[0058] FIGS. 6(1)-6(5) are first schematics including sectional viewsshowing steps of manufacturing the electro-optical device step by step;

[0059] FIGS. 7(b)-7(a) are second schematics including sectional viewsshowing steps of manufacturing the electro-optical device step by step;

[0060]FIG. 8 is a plan view showing a TFT array substrate, included inthe electro-optical device according to an exemplary embodiment of thepresent invention, having various components thereon, when viewed from acounter substrate;

[0061]FIG. 9 is a sectional view taken along the plane H-H′ of FIG. 8;

[0062]FIG. 10 is a schematic sectional view showing a liquid crystalprojector, which is an example of a projective color display unitincluded in an electronic apparatus according to an exemplary embodimentof the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0063] Embodiments of the present invention will now be described withreference to the accompanying figures. In the exemplary embodimentsdescribed below, an electro-optical device of an aspect of the presentinvention functions as a liquid crystal device.

[0064] Configuration of Pixel Portion

[0065] A configuration of each pixel portion of an electro-opticaldevice according to an exemplary embodiment of the present invention isdescribed with reference to FIGS. 1 to 4. FIG. 1 is a schematic showingan equivalent circuit including various elements and wiring lines forpixels arranged in a matrix, which constitute an image display region ofthe electro-optical device. FIG. 2 is a plan view showing a plurality ofthe pixels, adjacent to each other, placed on a TFT array substratehaving data lines, scanning lines, and pixel electrodes thereon. FIG. 3is a plan view showing only a principal portion of FIG. 2. Inparticular, FIG. 3 is a plan view showing the arrangement of the datalines, shielding layers, and pixel electrodes. FIG. 4 is a sectionalview taken along the plane A-A′ of FIG. 2. In FIG. 4, in order to showlayers and members on a recognizable scale, different scales are useddepending on the size of the layers and members.

[0066] With reference to FIG. 1, a plurality of the pixels are arrangedin a matrix, in which constitute the image display region of theelectro-optical device of this exemplary embodiment, and each includecorresponding pixel electrodes 9 a and TFTs 30 for controlling theswitching of the pixel electrodes. Data lines 6 a to which image signalsS1, S2, . . . , and Sn are transmitted are each electrically connectedto corresponding sources of the TFTs 30. The image signals S1, S2, . . ., and Sn written in the data lines 6 a may be line-sequentiallytransmitted to the data lines 6 a in this order or may be transmitted toeach group of the data lines 6 a adjacent to each other.

[0067] Gate electrodes are each electrically connected to correspondinggates of the TFTs 30, and scanning signals G1, G2, . . . , and Gm areline-sequentially applied to scanning lines 11 a and the gate electrodesin this order at a predetermined timing in an intermittent mode. Thepixel electrodes 9 a are electrically connected to drains of the TFTs30, and the image signals S1, S2, . . . , and Sn transmitted from thedata lines 6 a are written into with the pixel electrodes 9 a at apredetermined timing by turning on the TFTs 30 functioning as switchingelements for a predetermined period.

[0068] The image signals S1, S2, . . . , and Sn recorded in the liquidcrystals, which are an example of an electro-optical material, throughthe pixel electrodes 9 a have a predetermined level and are retainedbetween the pixel electrodes 9 a and a counter electrode disposed on acounter substrate for a predetermined period. When the alignment andorder of liquid crystal molecules are changed depending on the level ofapplied voltages, the liquid crystals modulate light, thereby displayingshades of gray. In a normally white mode, the transmittance of incidentlight is decreased in reverse proportion to the voltage applied eachpixel. In a normally black mode, the transmittance of incident light isincreased in proportion to the voltage applied each pixel. Thereby, as awhole, light having contrast depending on the image signals S1, S2, . .. , and Sn is emitted from the electro-optical device.

[0069] In order to reduce or prevent the retained image signals S1, S2,. . . , and Sn from leaking, storage capacitors 70 are each placed inparallel to corresponding liquid crystal capacitors disposed between thepixel electrodes 9 a and the counter electrode. The storage capacitors70 are each placed adjacent to the corresponding scanning lines 11 a andeach include constant potential capacitor electrodes and capacitorelectrodes 300 that are connected to a constant voltage power supply.

[0070] An actual configuration of the electro-optical device isdescribed below with reference to FIGS. 2 to 4. In the electro-opticaldevice, the circuit operation described above can be achieved using thedata lines 6 a, scanning lines 11 a, gate electrodes, and TFTs 30.

[0071] With reference to FIG. 2, a plurality of the pixel electrodes 9 a(the outline is indicated by a dotted line) are arranged on a TFT arraysubstrate 10 in a matrix. The data lines 6 a and scanning lines 11 aextend along the vertical and horizontal boundaries between the pixelelectrodes 9 a, respectively. The data lines 6 a have a layeredstructure including an aluminum film and the like, as described below.The scanning lines 11 a include, for example, a conductive polysiliconfilm or the like. The scanning lines 11 a are each electricallyconnected to corresponding gate electrodes 3 a facing channel regions 1a′ of corresponding semiconductor layers 1 a, the channel regions 1 a′being indicated by the right-upward diagonal lines in the figure. Thegate electrodes 3 a are each included in the corresponding scanninglines 11 a. The TFTs 30 to switch the pixels are each placed at thecorresponding intersections of the gate electrodes 3 a and data lines 6a and each include the corresponding gate electrodes 3 a which areincluded in the scanning lines 11 a that face the channel regions 1 a′.That is, the TFTs 30 (except for the gate electrodes 3 a) are eachplaced between the corresponding gate electrodes 3 a and scanning lines11 a.

[0072] Next, with respect to FIG. 4, which is a sectional view takenalong the plane A-A′ of FIG. 2, the electro-optical device includes theTFT array substrate 10 made of, for example, quartz, glass, or siliconand a counter substrate 20 that faces the TFT array substrate 10 and ismade of, for example, glass or silicon.

[0073] As shown in FIG. 4, the pixel electrodes 9 a are disposed on theTFT array substrate 10, and a first alignment layer 16 treated by apredetermined process, such as a rubbing process, is placed on the pixelelectrodes 9 a. The pixel electrodes 9 a include, for example, atransparent conductive film, such as an ITO film. On the other hand, acounter electrode 21 is placed over the entire surface of the countersubstrate 20, and a second alignment layer 22 treated by a predeterminedprocess, such as a rubbing process, is placed under the counterelectrode 21. The counter electrode 21, similarly to the pixelelectrodes 9 a, include, for example, a transparent conductive film,such as an ITO film. The first and second alignment layers 16 and 22contain, for example, a transparent organic material, such as polyimide.

[0074] In a space between the TFT array substrate 10, and the countersubstrate 20 facing the TFT array substrate 10, surrounded by a sealingmember 52 (see FIGS. 8 and 9) described below, electro-opticalsubstances, such as liquid crystals, is enclosed to form a liquidcrystal layer 50. The liquid crystal layer 50 takes a predeterminedalignment state due to the first and second alignment layers 16 and 22when no electric field is applied to the liquid crystal layer 50 fromthe pixel electrodes 9 a. The liquid crystal layer 50 containselectro-optical substances containing, for example, one or more speciesof nematic liquid crystals. The sealing member 52 is used to join theTFT array substrate 10 to counter substrate 20 and is placed at theperiphery thereof. The sealing member 52 contains an adhesive, such as aphotocurable resin, or a thermosetting resin and spacers, such as glassfibers or glass beads, to provide a predetermined distance between thesubstrates.

[0075] Various components may be disposed on the TFT array substrate 10in a stacked manner in addition to the pixel electrodes 9 and firstalignment layer 16, thereby forming a layered structure. With referenceto FIG. 4, the layered structure has a first level including thescanning lines 11 a, a second level including the TFTs 30 including thegate electrodes 3 a and the like, a third level including the storagecapacitors 70, a fourth level including the data lines 6 a and the like,a fifth level including a shielding layer 400 and the like, a sixth(uppermost) level including the pixel electrodes 9 a, the firstalignment layer 16 and the like, disposed in that order from the bottom.Furthermore, a base insulating layer 12 is placed between the first andsecond levels, a first interlayer insulating layer 41 is placed betweenthe second and third levels, a second interlayer insulating layer 42 isplaced between the third and fourth levels, a third interlayerinsulating layer 43 is placed between the fourth and fifth levels, and afourth interlayer insulating layer 44 is placed between the fifth andsixth levels, respectively, in order to reduce or prevent theabove-mentioned components from being short-circuited. These insulatinglayers 12, 41, 42, and 43 also have contact holes to electricallyconnect, for example, the data lines 6 a to heavily doped source regions1 d disposed in the semiconductor layers 1 a of the TFTs 30. Thesestacked components are described below in order from the bottom.

[0076] Firstly, the first level includes the scanning lines 11 aincluding a single metal substance, alloy, metal silicide orpolysilicide including at lease one of high-melting-point metalsselected from the group including titanium (Ti), chromium (Cr), tungsten(W), tantalum (Ta), and molybdenum (Mo); stacked layer thereof;conductive polysilicon, or the like. The scanning lines 11 a arearranged in parallel to the x-axis of FIG. 2 in a striped pattern whenviewed from above. In particular, each scanning line 11 a has a mainportion extending in parallel to the x-axis and protrusive portionsextending in parallel to the y-axis which is parallel to the data lines6 a and the shielding layer 400, as shown in FIG. 2. The protrusiveportions projecting from the scanning lines 11 a adjacent to each otherare not connected to each other; hence, the scanning lines 1 a areisolated from each other.

[0077] Thus, each scanning line 11 a has a function of simultaneouslyturning on or off the TFTs 30 placed in the same row. Furthermore, sincethe scanning lines 11 a extend so as to fill regions in which no pixelelectrodes 9 a are placed, the scanning lines 11 a have a function ofblocking light incident from the lower surfaces of the TFTs 30. Thereby,photo-leakage currents are reduced or prevented from being generated inthe semiconductor layers 1 a of the TFTs 30; hence, a high-quality imagewith no flicker can be displayed. When the scanning lines 11 a includeconductive polysilicon, the scanning lines 11 a have a function ofabsorbing light.

[0078] Next, the second level includes the TFTs 30 including the gateelectrodes 3 a. With reference to FIG. 4, the TFTs 30 have a lightlydoped drain (LDD) structure and each include the corresponding gateelectrodes 3 a, the corresponding semiconductor layers 1 a,corresponding insulating layers 2 to insulate the gate electrodes 3 afrom the semiconductor layers 1 a. The semiconductor layers 1 a eachinclude the corresponding channel regions 1 a′ made of a polysiliconfilm, for example, lightly doped source regions 1 b, lightly doped drainregions 1 c, heavily doped source regions 1 d, and heavily doped drainregions 1 e. In the channel regions 1 a′, channels are formed whenelectric fields are applied from the gate electrodes 3 a.

[0079] In particular, in this exemplary embodiment, the second levelfurther includes lower junction electrodes 719 formed using the samefilm as that for forming the gate electrodes 3 a. With reference to FIG.2, the lower junction electrodes 719 are each placed at substantiallythe corresponding center of one side of the pixel electrodes 9 a so asto have a dotted pattern. Since the lower junction electrodes 719 areformed using the same film as that used to form the gate electrodes 3 a,the lower junction electrodes 719 contain conductive polysilicon or thelike when the gate electrodes 3 a contain conductive polysilicon or thelike.

[0080] The TFTs 30 preferably have the LDD structure as shown in FIG. 4.However, the TFTs 30 may have an off-set structure without implantingimpurities into the lightly doped source regions 1 b and lightly dopeddrain regions 1 c or may have a self-aligned structure having heavilydoped source regions and heavily doped drain regions formed in aself-aligned manner by implanting impurities into regions of thesemiconductor layers 1 a at a high dose using the gate electrodes 3 a asmasks. Furthermore, in this exemplary embodiment, the TFTs 30 have asingle gate structure in which only one gate electrode 3 a is placedbetween each heavily doped source region 1 d and heavily doped drainregion 1 e. However, the TFTs 30 may have a double or more gatestructure having two or more of the gate electrodes 3 a placed betweenthese regions. When the TFTs 30 have the above-mentioned double gatestructure or triple or more gate structure, currents can be reduced orprevented from leaking at junctions of channels and source or drainregions, whereby the current consumed during the turning-off period canbe reduced.

[0081] Furthermore, the semiconductor layers 1 a included in the TFTs 30may be single-crystal or non-single-crystal layers. A known process,such as a cladding process, can be used to form such single crystallayers. When the semiconductor layers 1 a are the single crystal layers,the performance of peripheral circuits can be enhanced.

[0082] The base insulating layer 12 containing, for example, siliconoxide or the like is disposed between the scanning lines 11 a and theTFTs 30 disposed thereabove. The base insulating layer 12 insulates theTFTs 30 from the scanning lines 11 a. Furthermore, the base insulatinglayer 12 reduces or prevents properties of the TFTs 30 for switching thepixels from being deteriorated due to the surface roughness of the TFTarray substrate 10 caused by the surface polishing and contaminantsremaining after cleaning, because the base insulating layer 12 lies overthe TFT array substrate 10.

[0083] The base insulating layer 12 has slots 12 cv, disposed at bothsides of each semiconductor layer 1 a when viewed from above,functioning as contact holes. The slots 12 cv have the same length andwidth as those of channels of the semiconductor layers 1 a or a lengthlarger than that of the channels, wherein the semiconductor layers 1 aextend along the data lines 6 a as described below. The gate electrodes3 a placed above the slots 12 cv have recessed portions disposed atlower side thereof corresponding to the slots 12 cv. The gate electrodes3 a have side walls 3 b extending therefrom because the side walls 3 bare formed monolithically with the gate electrodes 3 a in such a mannerthat the slots 12 cv are filled with the same material as that used toform the gate electrodes 3 a. Thus, as shown in FIG. 2, sides of eachsemiconductor layer 1 a of the TFTs 30 are each covered with thecorresponding side walls 3 b, and therefore light is reduced orprevented from entering at least from these portions.

[0084] The side walls 3 b fill the corresponding slots 12 cv and thelower ends of the side walls 3 b contact with the scanning lines 11 a.Since the external electrodes 11 are arranged in a striped pattern asdescribed above, the gate electrodes 3 a and scanning lines 11 a placedin the same row always have the same potential.

[0085] In an aspect of the present invention, additional scanning linesincluding the gate electrodes 3 a may be arranged in parallel to thescanning lines 11 a. In this configuration, the scanning lines 11 a, andadditional scanning lines, form a redundant wiring structure.

[0086] Thus, even if some of the scanning lines 11 a have defects andtherefore normal conductance is not available, the TFTs 30 can benormally controlled through the additional scanning lines placed in thesame row as that of the scanning lines 11 a as long as the additionalscanning lines have no defects.

[0087] The third level includes the storage capacitors 70. The storagecapacitors 70 each include corresponding lower electrodes 71 functioningas the pixel potential capacitor electrodes, the corresponding capacitorelectrodes 300 functioning as the constant potential capacitorelectrodes, and corresponding dielectric layers 75 each disposed betweenthe corresponding lower electrodes 71 and capacitor electrodes 300. Thelower electrodes 71 each face the corresponding capacitor electrodes 300and are each connected to the corresponding heavily doped drain regions1 e and pixel electrodes 9 a of the TFTs 30. According to the storagecapacitors 70, potential-retaining properties of the pixel electrodes 9a can be greatly enhanced. With reference to FIG. 2, the storagecapacitors 70 of this exemplary embodiment do not extend tolight-transmitting regions which substantially correspond tolight-transmitting regions, that is, the storage capacitors 70 areplaced within light-shielding regions so that this electro-opticaldevice can have a relatively large aperture ratio as a whole, and thuscan display brighter images.

[0088] In particular, the lower electrodes 71 include a conductivepolysilicon film and function as the pixel potential capacitorelectrodes. However, the lower electrodes 71 may include a single layerfilm or a multi-layer film containing a metal or alloy. The lowerelectrodes 71 not only function as the pixel potential capacitorelectrodes but also each electrically connect the corresponding pixelelectrodes 9 a to the corresponding heavily doped drain regions 1 e ofthe TFTs 30. This exemplary embodiment is characterized in that theabove electrical connection is established via the lower junctionelectrodes 719. This feature is described below.

[0089] The capacitor electrodes 300 function as the constant potentialcapacitor electrodes of the storage capacitors 70. In this exemplaryembodiment, in order to allow the capacitor electrodes 300 to have aconstant potential, the capacitor electrodes 300 are electricallyconnected to the shielding layer 400 having a constant potential.

[0090] Particularly in this exemplary embodiment, the capacitorelectrodes 300 are arranged on the TFT array substrate 10 in a dottedpattern such that the capacitor electrodes 300 correspond to the pixels.The lower electrodes 71 have substantially the same shape as that of thecapacitor electrodes 300.

[0091] Thus, the storage capacitors 70 of this exemplary embodiment donot occupy unnecessarily large space, that is, do not lower the pixelaperture ratio while the storage capacitors 70 have an optimumcapacitance under the above circumstances. That is, the storagecapacitors 70 of this exemplary embodiment occupy a smaller space but alarger capacitance.

[0092] In particular, as shown in FIG. 4, the capacitor electrodes 300have an area slightly larger than that of the lower electrodes 71, thatis, the capacitor electrodes 71 each cover the corresponding lowerelectrodes 71. According to this configuration, as is clear from thefigure, sides of the capacitor electrodes 300 and lower electrodes 71can be used as capacitors (see a left region of each storage capacitor70 shown in FIG. 4), thereby enhancing the capacitance. A short circuitbetween them hardly occurs. From this viewpoint, in order to increasethe area of the sides, it is also effective that, for example, the lowerelectrodes 71 have a relatively large thickness.

[0093] With reference to FIG. 4, the dielectric layers 75 are made of arelatively thin silicon nitride or silicon dioxide film, such as a hightemperature oxide (HTO) or low temperature oxide (LTO) film, having athickness of 5 to 20 nm, for example. In order to increase thecapacitance of the storage capacitors 70, it is preferable to reduce thethickness of the dielectric layers 75 as long as the reliability of thedielectric layers 75 is obtained. As shown in FIG. 4, particularly inthis exemplary embodiment, the dielectric layers 75 have a double layerstructure including a silicon dioxide sub-layer 75 a as a lower layerand a silicon nitride sub-layer 75 b as an upper layer. The siliconnitride sub-layers 75 b, which are upper sub-layers, have a sizeslightly larger than that of the lower electrodes 71 functioning as thepixel potential capacitor electrodes and are each placed within thelight-shielding regions (non-aperture regions). According to such aconfiguration, the storage capacitors 70 can have a large capacitancebecause of the presence of the silicon nitride sub-layers 75 b having arelatively large dielectric constant, and yet the dielectric strength ofthe storage capacitors 70 is not lowered because of the presence of thesilicon dioxide sub-layer 75 a. Since the dielectric layers 75 have suchdouble layer structure, the above two conflicting advantages can beachieved. The silicon nitride sub-layers 75 b, which are apt to becolored, have a size slightly larger than that of the lower electrodes71 and not placed in the light-transmitting regions. That is, thesilicon nitride sub-layers 75 b are placed within the light-shieldingregions, thereby reducing or preventing the transmittance from beinglowered. Furthermore, the silicon nitride sub-layers 75 b reduces orprevents water from entering the TFTs 30. Thereby, in this exemplaryembodiment, the threshold voltage of the TFTs 30 is reduced or preventedfrom being increased and therefore the electro-optical device can beoperated for a long period. In this exemplary embodiment, the dielectriclayers 75 have the double layer structure. However, the dielectriclayers 75 may have a triple or more layer structure including, forexample, silicon dioxide sub-layers and a silicon nitride sub-layerdisposed therebetween if appropriate.

[0094] The first interlayer insulating layer 41 is placed on the TFTs 30or the gate electrodes 3 a and the lower junction electrodes 719, andunder the storage capacitors 70. The first interlayer insulating layer41 includes silicate glass, such as nondoped silicate glass (NSG),phosphorus silicate glass (PSG), boron silicate glass (BSG), or boronphosphorus silicate glass (BPSG); silicon nitride; or silicon dioxide.The first interlayer insulating layer 41 used herein preferably containsNSG The first interlayer insulating layer 41 has first contact holes 81,extending therethrough, to each electrically connect the correspondingheavily doped source regions 1 d of the TFTs 30 to the correspondingdata lines 6 a described below, wherein the first contact holes 81further extend through the second interlayer insulating layer 42. Thefirst interlayer insulating layer 41 also has second contact holes 83 toeach electrically connect the corresponding heavily doped drain regions1 e of the TFTs 30 to the corresponding lower electrodes 71 of thestorage capacitors 70.

[0095] The first interlayer insulating layer 41 further has thirdcontact holes 881, extending therethrough, to each electrically connectthe corresponding lower electrodes 71 which are the pixel potentialelectrodes of the storage capacitors 70 to the corresponding lowerjunction electrodes 719. The first interlayer insulating layer 41further has fourth contact holes 882, extending through the secondinterlayer insulating layer described below, to each electricallyconnect the corresponding lower junction electrodes 719 to secondjunction electrodes 6 a 2 described below.

[0096] The dielectric layers 75 are not placed in regions in which thefirst contact holes 81 and fourth contact holes 882 among the above fourkinds of contact holes are placed, that is, aperture regions are eachplaced on the corresponding dielectric layers 75. This is because thefirst contact holes 81 must be each used to electrically connect thecorresponding heavily doped source regions 1 d to the corresponding datalines 6 a and the fourth contact holes 882 must extend through the firstand second interlayer insulating layers 41 and 42. If such apertures areprovided in the dielectric layers 75, when hydrotreatment is carried outon the semiconductor layers 1 a of the TFTs 30, hydrogen can be readilydelivered to the semiconductor layers 1 a through the apertures.

[0097] In this exemplary embodiment, the first interlayer insulatinglayer 41 may be fired at about 1,000° C., thereby activating ionsimplanted into polysilicon films included in the semiconductor layers 1a or gate electrodes 3 a.

[0098] The fourth level disposed on the third level includes the datalines 6 a. The data lines 6 a are arranged in a striped pattern suchthat they extend in the same direction as the semiconductor layers 1 aextend, that is, in parallel to the y-axis in FIG. 2. With reference toFIG. 4, each data line 6 a has a triple layer structure including analuminum film (see 41A in FIG. 4), a titanium nitride film (see 41TN inFIG. 4), and a silicon nitride film (see 401 in FIG. 4) disposed in thisorder from the lower side. The silicon nitride film 401 has a sizeslightly larger than that of the titanium nitride film 41TN and aluminumfilm 41A so as to cover the titanium nitride film 41TN and aluminum film41A. Since the data lines 6 a contain aluminum having a relatively smallresistance, image signals can be smoothly transmitted to the TFTs 30 andthe pixel electrodes 9 a. Furthermore, since the date lines 6 a includethe silicon nitride films 401 having a relatively excellent function ofblocking water penetration, the TFTs 30 can be enhanced in moistureresistance properties, thereby extending the life of the TFTs 30. Thesilicon nitride films 401 are preferably formed by a plasma CVD process.

[0099] The fourth level further includes first junction electrodes 6 a 1and second junction electrodes 6 a 2, the first and second junctionelectrodes 6 a 1 and 6 a 2 being formed using the same film as that usedto form the data lines 6 a. With reference to FIG. 2, the first andsecond junction electrodes 6 a 1 and 6 a 2 are not continuously formedwith the corresponding data lines 6 a when viewed from above, that is,these components are arranged in independent patterns. In a left area ofFIG. 2, each data line 6 a, first junction electrode 6 a 1, and secondjunction electrode 6 a 2 are arranged in this order from the left,wherein the first junction electrode 6 a 1 has a substantiallyrectangular shape and the second junction electrode 6 a 2 has asubstantially rectangular shape and an area slightly larger than that ofthe first junction electrode 6 a 1. The first and second junctionelectrodes 6 a 1 and 6 a 2 are formed in the same step as that forforming the data lines 6 a, and therefore have the triple layerstructure including each aluminum film 41A, titanium nitride film 41TN,and plasma silicon nitride film 401 disposed in this order from thelower layer.

[0100] The plasma silicon nitride films 401 have a size slightly largerthan that of the titanium nitride films 41TN and aluminum films 41A soas to cover the corresponding titanium nitride films 41TN and aluminumfilms 41A. The plasma silicon nitride films 401 function as barriermetal films to prevent the first and second junction electrodes 6 a 1and 6 a 2 from being penetrated when fifth and sixth contact holes 803and 804 are formed in the third interlayer insulating layer 43 by anetching process.

[0101] Furthermore, since the silicon nitride films 401 are each locatedat the top of the corresponding first junction electrodes 6 a 1 andsecond junction electrodes 6 a 2 and have a function of blocking waterpenetration, the TFTs 30 can be enhanced in the moisture resistanceproperties, thereby achieving long life of the TFTs 30. The siliconnitride films 401 are preferably formed by a plasma CVD process.

[0102] The second interlayer insulating layer 42 is placed on thestorage capacitors 70 and is placed under the data lines 6 a. The secondinterlayer insulating layer 42 contains silicate glass, such as NSG;PSG, BSG, or BPSG; silicon nitride; or silicon dioxide. The secondinterlayer insulating layer 42 used herein is preferably formed by aplasma CVD process using TEOS gas. The second interlayer insulatinglayer 42 has the first contact holes 81, extending therethrough, eachelectrically connecting the corresponding heavily doped source regions 1d of the TFTs 30 to the corresponding data lines 6 a. The secondinterlayer insulating layer 42 further has seventh contact holes 801,extending therethrough, for each electrically connecting thecorresponding first junction electrodes 6 a 1 to the correspondingcapacitor electrodes 300 functioning as the upper electrodes of thestorage capacitors 70. Furthermore, the second interlayer insulatinglayer 42 has the fourth contact holes 882, extending therethrough, foreach electrically connecting the corresponding lower junction electrodes719 to the corresponding second junction electrodes 6 a 2.

[0103] The fifth level disposed on the fourth level includes theshielding layer 400. With reference to FIGS. 2 and 3, the shieldinglayer 400 has a grid pattern and extends in parallel to the x andy-axes. The portions of the shielding layer 400 extending in parallel tothe y-axis are particularly formed such that they have a width largerthan that of the data lines 6 a and cover the data lines 6 a. Theportions of the shielding layer 400 extending in parallel to the x axiseach have corresponding notches, each disposed near the center of a sideof each pixel electrode 9 a, to secure regions to form third junctionelectrodes 402 described below.

[0104] Furthermore, substantially triangular sections are each disposedat corresponding corners of each intersection of the shielding layerportions extending in parallel to the x- and y-axes in FIGS. 2 and 3.Since the shielding layer 400 has the substantially triangular sections,light can be securely reduced or prevented from entering thesemiconductor layers 1 a of the TFTs 30. That is, light incident on thesemiconductor layers 1 a from a diagonal upward direction is reflectedor absorbed by the triangular sections, thereby not reaching thesemiconductor layers 1 a. Thus, photo-leakage currents are reduced orprevented from being generated, whereby a high-quality image with noflicker can be displayed.

[0105] The shielding layer 400 extends from the image display region 10a having the pixel electrodes 9 a therein to the peripheral areas. Theshielding layer 400 is electrically connected to a constant potentialpower source to have a constant potential. The “constant potential powersource” may be a positive or negative constant potential power sourceelectrically connected to a data line-driving circuit 101, or anotherconstant potential power source electrically connected to the counterelectrode 21 on the counter substrate 20.

[0106] Since the shielding layer 400 is formed to entirely cover thedata lines 6 a as shown in FIG. 3 and has a constant potential in thisway, an influence of capacitance coupling occurring between the datalines 6 a and pixel electrodes 9 a can be eliminated. That is, thepotential of the pixel electrodes 9 a can be reduced or prevented fromfluctuating in accordance with current application to the data lines 6a. Therefore, uneven display can be reduced or prevented from beingformed along the data lines 6 a on a screen. Particularly in thisexemplary embodiment, since the shielding layer 400 has a grid pattern,undesirable capacitance coupling can be reduced or prevented fromoccurring in regions in which the scanning lines 11 a extend.

[0107] Furthermore, in the fourth level, third junction electrodes 402,an example of the junction electrodes specified herein, are formed usingthe same film used to form the shielding layer 400. The third junctionelectrodes 402 are each used to electrically connect the correspondingsecond junction electrodes 6 a 2 to the corresponding pixel electrodes 9a through eighth contact holes 89 described below. The shielding layer400 is not continuously formed with the third junction electrodes 402but is isolated from the third junction electrodes 402 when viewed fromabove.

[0108] On the other hand, the shielding layer 400 and third junctionelectrodes 402 each have a double layer structure including a loweraluminum film and an upper titanium nitride film disposed in this order.In the third junction electrodes 402, the lower aluminum films are eachelectrically connected to the corresponding second junction electrodes 6a 2, while the upper titanium nitride films are each electricallyconnected to the corresponding pixel electrodes 9 a containing ITO orthe like. In this configuration, the titanium nitride films can besecurely connected to the pixel electrodes 9 a in particular. On thecontrary, if each aluminum film is directly connected to each pixelelectrode 9 a containing ITO, galvanic corrosion occurs therebetween,and an electrical connection cannot be securely established therebetweendue to breaking of the aluminum film or insulation caused by theformation of alumina. In this exemplary embodiment, since the thirdjunction electrodes 402 can be securely connected to the pixelelectrodes 9 a as described above, it is possible to appropriately applya voltage to the pixel electrodes 9 a or to hold the potential-retainingproperties of the pixel electrodes 9 a satisfactorily.

[0109] Furthermore, since the shielding layer 400 and third junctionelectrodes 402 contain aluminum having a relatively excellent lightreflecting property and titanium nitride having a relatively excellentlight absorbing property, the shielding layer 400 and third junctionelectrodes 402 can function as light-shielding layers. That is,according to this configuration, light incident on the semiconductorlayers 1 a of the TFTs 30 (see FIG. 4) can be blocked above thesemiconductor layers 1 a of the TFTs 30. In the above-mentionedcapacitor electrodes 300 and data lines 6 a, the same advantage as thiscan be obtained. In this exemplary embodiment, the shielding layer 400,third junction electrodes 402, capacitor electrodes 300, and data lines6 a form part of the layered structure disposed on the TFT arraysubstrate 10 and can function as upper light-shielding layers to shieldthe TSTs 30 against light entering from the upper side. The upperlight-shielding layers may be referred to as “built-in light-shieldinglayers” because the shielding layer 400, third junction electrodes 402,capacitor electrodes 300, and data lines 6 a are components of thelayered structure. Incidentally, according to this concept, the “upperlight-shielding layers”, or the “built-in light-shielding layers” alsoinclude the gate electrodes 3 a and lower electrodes 71 in addition tothe above components. Under the broadest definition, any component,placed on the TFT array substrate 10, including an opaque material maybe referred to as the “upper light-shielding layers”, or the “built-inlight-shielding layers”.

[0110] The third interlayer insulating layer 43 is placed on theabove-mentioned data lines 6 a and placed under the shielding layer 400.The third interlayer insulating layer 43 contain silicate glass, such asNSG, PSG, BSG or BPSG; silicon nitride; or silicon dioxide. The thirdinterlayer insulating layer 43 used herein is preferably formed by aplasma CVD process using TEOS gas. The third interlayer insulating layer43 has ninth contact holes 803, extending therethrough, eachelectrically connecting the shielding layer 400 to the correspondingfirst junction electrodes 6 a 1 and sixth contact holes 804, extendingtherethrough, each electrically connecting the corresponding thirdjunction electrodes 402 to the corresponding second junction electrodes6 a 2.

[0111] In contrast to the first interlayer insulating layer 41, thesecond interlayer insulating layer 42 may not be subjected to firing soas to ease stress occurring in the interfaces between the capacitorelectrodes 300 and second interlayer insulating layer 42.

[0112] Finally, in the sixth level, the pixel electrodes 9 a arearranged in a matrix and the first alignment layer 16 is disposedthereon. The fourth interlayer insulating layer 44 is disposed under thepixel electrodes 9 a. The fourth interlayer insulating layer 44 containssilicate glass, such as NSG PSG, BSG, or BPSG; silicon nitride; silicondioxide; or the like, and preferably contains BPSG The fourth interlayerinsulating layer 44 has the eighth contact holes 89, extendingtherethrough, each electrically connecting the pixel electrodes 9 a tothe third junction electrodes 402. Particularly in this exemplaryembodiment, the surface of the fourth interlayer insulating layer 44 isplanarized by a chemical mechanical polishing (CMP) process or the like,whereby misorientation of the liquid layer 50 due to steps can bereduced, the steps being caused by various wiring lines and/or elementsdisposed under the fourth interlayer insulating layer 44. However,instead of or in addition to such planarization of the fourth interlayerinsulating layer 44, may be formed in at least one of the, TFT arraysubstrate 10, base insulating layer 12, first interlayer insulatinglayer 41, second interlayer insulating layer 42, and third interlayerinsulating layer 43, to bury the TFTs 30 and wiring lines, such as thedata lines 6 a therein.

[0113] In this exemplary embodiment, the electro-optical device havingthe above configuration is characterized in that the second levelincludes the lower junction electrodes 719 formed using the same film asthat for forming the gate electrodes 3 a, and the lower electrodes 71 ofthe storage capacitors 70 located in the third level are eachelectrically connected to the corresponding pixel electrodes 9 a locatedin the sixth level with the corresponding lower junction electrodes 719.

[0114] As described above, the lower electrodes 71 and the pixelelectrodes 9 a are electrically connected to each other with the lowerjunction electrodes 719 located below the lower electrodes 71 and pixelelectrodes 9 a. Thus, electrical contacts of the lower junctionelectrodes 719 and the lower electrodes 71, especially the electricalcontacts of the lower electrodes 71 are located below the lowerelectrodes 71 when focused the positions of the lower electrodes 71 (seethe third contact holes 881 shown in FIG. 4).

[0115] Since the electro-optical device of this exemplary embodiment hasthe above configuration, advantages described below can be obtained.Such advantages can be made clear by comparing the presentelectro-optical device with a comparative electro-optical device havinga configuration different from the above-mentioned configuration. Thecomparison is made below with reference to FIG. 5. FIG. 5 is a sectionalview showing the comparative electro-optical device to be compared withthe present electro-optical device shown in FIG. 4. In order tofacilitate description, the substantially same components shown in FIG.5 as those shown in FIG. 4. have the same reference numerals as those ofthe components shown in FIG. 4. The comparative electro-optical deviceis merely used for the comparison with the electro-optical deviceaccording to the exemplary embodiment described above and is within thescope of the present invention.

[0116] First of all, with reference to FIG. 4, as described above, thelower electrodes 71 and lower junction electrodes 719 are electricallyconnected to each other through the third contact holes 881 extendingthrough the first interlayer insulating layer 41 disposed between thelower electrodes 71 and lower junction electrodes 719. Thus, theelectrical contacts of the lower junction electrodes 719 and the lowerelectrodes 71 are located “below” the lower electrodes 71.

[0117] In contrast, with reference to FIG. 5, there are no lowerjunction electrodes 719; hence, comparative lower electrodes 71′ and thepixel electrodes 9 a are electrically connected to each other throughcomparative contact holes 8821 having electrical contacts disposed abovethe comparative lower electrodes 71′. In particular, the comparativecontact holes 8821 extend through the second interlayer insulating layer42 and the dielectric layers 75, and comparative second junctionelectrodes 6 a 21 are formed on the second interlayer insulating layer42 and fill the comparative contact holes 8821. A configuration locatedabove these components is substantially the same as that shown in FIG.4.

[0118] In the comparative electro-optical device having the aboveconfiguration, in order to electrically connect the comparative lowerelectrodes 71′ to the respective pixel electrodes 9 a, regions locatedabove the comparative lower electrodes 71′ must be used, as is clearfrom FIG. 5. Furthermore, in order to form such a configuration, “only”the dielectric layers 75 and the capacitor electrodes 300, which arecomponents of comparative storage capacitors 70′, must be etched in thiscase (see the areas indicated by the broken lines in FIG. 5). This isbecause the surfaces of the comparative lower electrodes 71′ must beexposed when viewed from above in order to electrically connect thecomparative lower electrodes 71′ and pixel electrodes 9 a each other.

[0119] However, such etching treatment is difficult, because thecomparative lower electrodes 71′ and dielectric layers 75 usually have athickness as small as possible. Furthermore, in this exemplaryembodiment, the dielectric layers 75 each include the correspondingsilicon nitride films and the like, and therefore the silicon dioxidefilms are thinner by that much. When, for example, the capacitorelectrodes 300 include polysilicon, tungsten silicide or stacked layerthereof, the capacitor electrodes 300 can be etched by setting theetching rate of the silicon dioxide films included in the dielectriclayers 75 considerably smaller than that of the capacitor electrodes 300to stop the etching on the dielectric layers 75. However, the dielectriclayers 75 are penetrated by etching and the pixel potential capacitorelectrodes are also easily etched when the silicon dioxide filmsincluded in the dielectric layers 75 have a small thickness. Thus, inthis configuration, so-called “penetrations” or the like are probablycaused in the comparative lower electrodes 71′. Therefore, there is aproblem in that the capacitor electrodes 300 and comparative lowerelectrodes 71′, which are components of the storage capacitors 70, areshort-circuited at the worst.

[0120] However, in this exemplary embodiment, such a difficult etchingstep is not necessary, as shown in FIG. 4, and therefore the lowerelectrodes 71 can be each electrically connected to the correspondingpixel electrodes 9 a securely. The lower electrodes 71 and pixelelectrodes 9 a are electrically connected to each other with thecorresponding lower junction electrodes 719. Furthermore, in thisexemplary embodiment, for the same reason as the above, the capacitorelectrodes 300 and lower electrodes 71 are hardly short-circuited. Thus,the storage capacitors 70 having no defects can be preferably formed.

[0121] As described above, in this exemplary embodiment, the storagecapacitors 70 can be electrically connected to the pixel electrodes 9 asecurely and the risk that the storage capacitors 70 have defects isgreatly reduced. Thus, the electro-optical device which operates muchbetter can be obtained.

[0122] In this exemplary embodiment, the lower junction electrodes 719are formed using the same film used to form the gate electrodes 3 a;however, the present invention is not limited to this exemplaryembodiment. For example, the third level includes the storage capacitors70 in this exemplary embodiment; however, another layer disposed abovethe third level may include the storage capacitors 70 according toneeds. In such a case, the lower junction electrodes 719 may be disposedin an upper level relative to the gate electrodes 3 a. For the two- orthree-dimensional arrangement of the various components of theelectro-optical device, the present invention is not limited to theabove-mentioned exemplary embodiment. Various arrangements thereofdifferent from those shown in FIGS. 1 to 4 may be employed.

[0123] In this exemplary embodiment, the storage capacitors 70 have thetriple layer structure including each pixel potential capacitorelectrode, dielectric layer, and constant potential capacitor electrodedisposed in this order from the bottom; however, these components may bedisposed in an order reverse to the above order according to needs. Inthis configuration, the pixel potential capacitor electrode, functioningas an upper electrode, preferably has an area larger than that of theconstant potential capacitor electrode. For example, the pixel potentialcapacitor electrode preferably has a region extending out of theconstant potential capacitor electrode in plan view. The extendingregion is preferably disposed corresponding to a region to form acontact hole extending to the lower junction electrode 719. According tothis configuration, the lower junction electrode 719 can be electricallyconnected to the pixel potential capacitor electrode readily throughthis contact hole.

[0124] Thus, the “pixel potential capacitor electrodes” specified hereinneed not constitute the “lower” electrodes 71 of the storage capacitors70 as described in this exemplary embodiment, but may constitute theupper electrodes thereof.

[0125] Manufacturing Process

[0126] A process to manufacture an electro-optical device similar to theabove exemplary embodiment will now be described with reference to FIGS.6 and 7. FIGS. 6 and 7 each include sectional views showing steps ofmanufacturing the electro-optical device according to this exemplaryembodiment step by step.

[0127] As shown in (FIG. 6(1), the TFT array substrate 10 containingquartz, hard glass, or silicon is prepared. The TFT array substrate 10is then pretreated. For example, the TFT array substrate 10 ispreferably annealed at a high temperature ranging from about 900 to1,300° C. in an inert gas atmosphere preferably, such as nitrogen (N₂),so as to decrease deformation of the TFT array substrate 10 caused insubsequent steps at a high temperature.

[0128] A first precursor film is formed over the entire surface of theresulting TFT array substrate 10 by a sputtering process. The firstprecursor film contains a metal, such as Ti, Cr, W, Ta, or Mo; or metalalloy, such as a metal silicide containing such metals as describedabove and has a thickness of about 100 to 500 nm, preferably 200 nm. Thefirst precursor film is then subjected to photolithography and etching,thereby forming the scanning lines 11 a arranged in a striped patternwhen viewed from above. The base insulating layer 12 is formed on thescanning lines 11 a by an atmospheric or vacuum CVD process or the likeusing tetraethyl orthosilicate (TEOS) gas, tetraethyl borate (TEB) gas,or trimethyl orthophosphate (TMOP) gas. The base insulating layer 12 hasa thickness of about 500 to 2,000 run and contains silicate glass, suchas nondoped silicate glass (NSG), phosphorus silicate glass (PSG), boronsilicate glass (BSG), or boron phosphorus silicate glass (BPSG); siliconnitride; or silicon dioxide.

[0129] Then, an amorphous silicon layer is formed on the base insulatinglayer 12 at a relatively low temperature ranging from 450 to 550° C.,preferably about 500° C. (at a pressure of about 20 to 40 Pa) by avacuum CVD process using monosilane gas or disilane gas. The flow rateof the monosilane or disilane gas is about 400 to 600 cc/min. Theamorphous silicon layer is then heat-treated for about 1 to 10 hours,preferably 4 to 6 hours, at about 600 to 700° C. in a nitrogen gasatmosphere, whereby a polysilicon (p-Si) layer having a thickness ofabout 50 to 200 nm, preferably about 100 nm, is formed by solid phaseepitaxy. The solid phase epitaxy may be carried out by an annealingprocess using RTA or by a laser annealing process using excimer laser orthe like. The polysilicon layer may be then slightly doped with adopant, such as a group V element or a group III element by ionimplantation depending on the type of the TFTs 30 for switching pixels:an n-channel type or a p-channel type. The polysilicon layer issubjected to photolithography and etching, whereby the semiconductorlayers 1 a are formed in a predetermined pattern.

[0130] Next, as shown in FIG. 6(2), the semiconductor layers 1 aincluded in the TFTs 30 are thermally oxidized at a temperature of about900 to 1,300° C., preferably about 1,000° C., thereby forming lowergate-insulating sub-layers. Upper gate-insulating sub-layers may besubsequently each formed on the corresponding lower gate-insulatingsub-layers by a vacuum CVD process or the like, if necessary. Thereby,insulating layers 2 that have a single- or multi-layer structure andcontain high temperature oxide (HTO) and/or silicon nitride are formed(the insulating layers 2 include the above gate-insulating sub-layers).As a result, the semiconductor layers 1 a have a thickness of about 30to 150 nm and preferably 35 to 50 nm. The insulating layers 2 have athickness of about 20 to 150 nm and preferably 30 to 100 nm.

[0131] In order to control the threshold voltage V_(th) of the TFTs 30to switch the pixels, n-channel regions or p-channel regions of thesemiconductor layers 1 a are doped with a predetermined amount ofdopant, such as boron by ion implantation or the like.

[0132] Then, the slots 12 cv extending to the scanning lines 11 a areformed in the base insulating layer 12 by a dry etching process, such asa reactive ion etching process or a reactive ion beam etching process.

[0133] As shown in FIG. 6(3), a polysilicon layer is deposited over thebase insulating layer 12 by a vacuum CVD process or the like, andphosphorus (P) is thermally diffused in the polysilicon layer, therebyrendering the polysilicon layer conductive. Alternatively, P ions may beintroduced into the polysilicon layer during the formation thereofinstead of the thermal diffusion, thereby forming a doped polysiliconlayer. The polysilicon layer preferably has a thickness of about 100 to500 nm and preferably about 350 nm. The resulting polysilicon layer isthen subjected to photolithography and etching, thereby forming the gateelectrodes 3 a, arranged in a predetermined pattern, including gateelectrode portions for the TFTs 30. According to the manufacturingprocess of the invention, when the gate electrodes 3 a are formed, theside walls 3 b extending from the gate electrodes 3 a are simultaneouslyformed. The side walls 3 b are formed by depositing the polysiliconlayer in the slots 12 cv. In this case, since the bottoms of the slots12 cv are in contact with the corresponding scanning lines 11 a, theside walls 3 b are each electrically connected to the correspondingscanning lines 11 a. Furthermore, according to the manufacturingprocess, the lower junction electrodes 719 are also formed during theformation of the gate electrodes 3 a. Thereby, the lower junctionelectrodes 719 are arranged in a two-dimensional pattern shown in FIG.2.

[0134] The following regions are then each formed in the correspondingsemiconductor layers 1 a: the lightly doped source regions 1 b, lightlydoped drain regions 1 c, heavily doped source regions 1 d, and heavilydoped drain regions 1 e.

[0135] A procedure to form the TFTs 30 that are of an n-channel type andhave an LDD structure is described below. In order to form the lightlydoped source regions 1 b and lightly doped drain regions 1 c, thesemiconductor layers 1 a are doped with a dopant of a group V element,such as P at a small dose using the gate electrodes 3 a as masks (forexample, P ions are implanted at a dose of 1×10¹³ to 3×10¹³/cm²).Thereby, a portion of each semiconductor layer 1 a disposed below eachgate electrode 3 a is transformed into a channel region 1 a′. In thisprocedure, the lightly doped source regions 1 b and lightly doped drainregions 1 c are formed in a self-aligned manner because the gateelectrodes 3 a function as masks.

[0136] Next, in order to form the heavily doped source regions 1 d andheavily doped drain regions 1 e, a resist layer having line portionshaving a width larger than that of the gate electrodes 3 a is formedover the gate electrodes 3 a. In such a state, the semiconductor layers1 a are doped with a dopant of a group V element, such as P at a highdose (for example, P ions are implanted at a dose of 1×10¹⁵ to3×10¹⁵/cm²).

[0137] The semiconductor layers 1 a need not be doped in two steps, lowdose implantation and high dose implantation. For example, TFTs havingoffset structure may be formed without performing the low doseimplantation. Alternatively, TFTs having self-aligned structure may beformed by the implantation of ions, such as P or B ions using the gateelectrodes 3 a as masks. The resistance of the gate electrodes 3 a isfurther decreased by the implantation of these impurity ions.

[0138] Next, as shown in (FIG. 6(4), the first interlayer insulatinglayer 41 is formed over the gate electrodes 3 a by an atmospheric orvacuum CVD process using TEOS gas, TEB gas, or TMOP gas or the like. Thefirst interlayer insulating layer 41 contains silicate glass, such asNSG PSG, BSG, or BPSG; silicon nitride; or silicon dioxide and has athickness of about 500 to 2,000 nm. The first interlayer insulatinglayer 41 is preferably annealed at a high temperature, for example,about 800° C., thereby enhancing properties thereof.

[0139] The second contact holes 83 and third contact holes 881 areformed in the first interlayer insulating layer 41 by a dry etchingprocess, such as a reactive ion etching process or a reactive ion beametching process. In this case, the second contact holes 83 each extendto the corresponding heavily doped drain regions 1 e, and the thirdcontact holes 881 extend to the corresponding lower junction electrodes719.

[0140] As shown in FIG. 6(5), a second precursor film for the lowerelectrodes 71 having a thickness of about 100 to 500 nm and apredetermined pattern is formed on the first interlayer insulating layer41 by sputtering Pt or the like. In this case, the second precursor filmis formed such that the second contact holes 83 and third contact holes881 are filled with such metal film. Thereby, the lower electrodes 71are each electrically connected to the corresponding heavily doped drainregions 1 e and lower junction electrodes 719. The second precursor filmis then etched, thereby forming the lower electrodes 71.

[0141] Subsequently, the dielectric layers 75 are each provided on thecorresponding lower electrodes 71 according to the procedure below. Likein the case of the insulating layers 2, the dielectric layers 75 can beformed by any suitable process generally used to form TFT gateinsulating layers. In this exemplary embodiment, first, the silicondioxide sub-layer 75 a is formed by the above-mentioned thermaloxidation process, CVD process, or the like, and then, the siliconnitride sub-layers 75 b are formed thereon by a plasma CVD process orthe like. Since the capacitance of the storage capacitors 70 becomeslarger as the dielectric layers 75 become thinner, the dielectric layers75 are preferably formed to have a small thickness, for example, athickness of 50 nm or less, as long as the dielectric layers 75 are notbroken. Then, a fourth precursor film, having a thickness of about 100to 500 nm, to form capacitor electrodes 300 is formed on the dielectriclayers 75 by sputtering a metal, such as Al.

[0142] As shown in FIG. 7(6), the silicon dioxide sub-layer 75 a is notetched but the third precursor film for the silicon nitride sub-layers75 b is etched such that the silicon nitride sub-layers 75 b have a sizeslightly larger than that of the lower electrodes 71 of the pixelpotential capacitor electrodes. Furthermore, the fourth precursor filmfor the capacitor electrodes 300 is then etched such that the capacitorelectrodes 300 have substantially the same size as that of the lowerelectrodes 71. In such a configuration, based on the formation of thecapacitor electrodes 300, the portions each disposed between thecorresponding capacitor electrodes 300 and lower electrodes 71substantially correspond to the dielectric layers 75 (see FIG. 4).

[0143] Alternatively, in FIG. 7(6), the third precursor film to form thesilicon nitride sub-layers 75 b and the fourth precursor film to formthe capacitor electrodes 300 may be etched in one step to form thedielectric layers 75 and capacitor electrodes 300, and to thereby obtainthe storage capacitors 70.

[0144] As described above, in this exemplary embodiment, the storagecapacitors 70 are formed such that the capacitor electrodes 300functioning as the constant potential capacitor electrodes have an arealarger than that of the dielectric layers 75 and that of the lowerelectrodes 71 functioning as the pixel potential capacitor electrodes.Therefore, the dielectric layers 75 are in contact with the capacitorelectrodes 300 with a large area. In particular, sides of the threecomponents of each storage capacitor 70 can be used as capacitorportions. Thus, it can be expected that the storage capacitors 70 have alarger capacitance. Namely, according to this exemplary embodiment, thestorage capacitors 70 having a relatively large capacitance, but nowasted area, can be formed without decreasing the pixel aperture ratio.Therefore, from this point of view, if the lower electrodes 71 areformed relatively thick, the area of the sides is increased, therebyenhancing the capacitance effectively. As is clear from the figure,according to this configuration, the dielectric layers 75 each cover thecorresponding lower electrodes 71, and therefore the risk that capacitorelectrode 300 and lower electrode 71 are short-circuited can be reduced.

[0145] Furthermore, according to this exemplary embodiment, sinceetching is performed as described above, the following difficulttechnique is not necessary in contrast to known methods: only thecapacitor electrodes 300 and dielectric layers 75 are etched while thelower electrodes 71 located below are remained as they are. Thus,according to an aspect of the present invention, reliable storagecapacitors can be readily manufactured.

[0146] As shown in FIG. 7(7), the second interlayer insulating layer 42is formed by an atmospheric or vacuum CVD process, preferably by aplasma CVD process, using, for example, TEOS gas or the like. The secondinterlayer insulating layer 42 contains silicate glass, such as NSG PSG,BSG or BPSG; silicon nitride; or silicon dioxide. When the capacitorelectrodes 300 contain aluminum, the second interlayer insulating layer42 must be formed at a low temperature by a plasma CVD process. Thesecond interlayer insulating layer 42 has a thickness of about 500 to1,500 nm. Then, the first contact holes 81, seventh contact holes 801,and fourth contact holes 882 are formed in the second interlayerinsulating layer 42 by a dry etching process, such as a reactive ionetching process or a reactive ion beam etching process. In this case,the first contact holes 81 each extend to the corresponding heavilydoped source regions 1 d of the semiconductor layers 1 a, the seventhcontact holes 801 each extend to the corresponding capacitor electrodes300, and the fourth contact holes 882 each extend to the correspondinglower junction electrodes 719.

[0147] As shown in FIG. 7(8), a fifth precursor film is formed on theentire surface of the second interlayer insulating layer 42 by asputtering process or the like. The fifth precursor film containslight-shielding and low resistant metal, such as aluminum, metalsilicide or the like and has a thickness of about 100 to 500 nm,preferably about 300 nm. The fifth precursor film is subjected tophotolithography and etching to form the data lines 6 a having apredetermined pattern. In this etching step, the first junctionelectrodes 6 a 1 and second junction electrodes 6 a 2 are alsosimultaneously formed. The first junction electrodes 6 a 1 each coverthe corresponding seventh contact holes 801, and the second junctionelectrodes 6 a 2 each cover the corresponding fourth contact holes 882.A titanium nitride film is then formed over these components by a plasmaCVD process or the like, and is etched such that the titanium nitridefilm remains only on the data lines 6 a (see reference numeral 41TNshown in FIG. 7(8)). However, the titanium nitride film may remain onthe corresponding first junction electrodes 6 a 1 and second junctionelectrodes 6 a 2 and the titanium nitride film may remain over theentire surface of the TFT array substrate 10. The titanium nitride filmand the fifth precursor film containing aluminum may be formedsimultaneously, and subjected to etching in one step. (In this case, anobtained configuration is somehow different from that shown in FIG. 4.)

[0148] As shown in FIG. 7(9), the third interlayer insulating layer 43is formed to cover the data lines 6 a and the like by an atmospheric orvacuum CVD process using, for example, TEOS gas or the like, preferablyby a plasma CVD process which allows film formation at a lowtemperature. The third interlayer insulating layer 43 contains silicateglass, such as NSG, PSG, BSG, or BPSG, silicon nitride, silicon dioxideor the like, and has a thickness of about 500 to 1,500 nm. The ninthcontact holes 803 and sixth contact holes 804 are formed in the thirdinterlayer insulating layer 43 by a dry etching process, such as areactive ion etching process or a reactive ion beam etching process. Theninth contact holes 803 are formed to lead to the corresponding firstjunction electrodes 6 a 1, and the sixth contact holes 804 are formed tolead to the corresponding second junction electrodes 6 a 2.

[0149] A shielding layer 400 is formed on the resulting third interlayerinsulating layer 43 by a sputtering process, plasma CVD process or thelike. The forming procedure is as follows: first, a first sub-layercontaining a material, such as aluminum, having a small resistance isformed; secondly, a second sub-layer is formed on the first sub-layer,the second sub-layer containing titanium nitride or a material whichdoes not generate galvanic corrosion with ITO constituting the pixelelectrodes 9 a described below; and finally, the first and secondsub-layers are etched together, thereby obtaining the shielding layer400 having a double layer structure. In this case, third junctionelectrodes 402 are formed simultaneously with the shielding layer 400.

[0150] Then, the fourth interlayer insulating layer 44 is formed by anatmospheric or vacuum CVD process using, for example, TEOS gas or thelike. The fourth interlayer insulating layer 44 contains silicate glass,such as NSG, PSG, BSG, or BPSG; silicon nitride, silicon dioxide or thelike, and has a thickness of about 500 to 1,500 nm. The eighth contactholes 89 are formed in the fourth interlayer insulating layer 44 by adry etching process, such as a reactive ion etching process or areactive ion beam etching process. In this case, the eighth contactholes 89 each extend to the corresponding third junction electrodes 402.

[0151] A transparent conductive layer, containing ITO or the like,having a thickness of about 50 to 200 nm is formed on the fourthinterlayer insulating layer 44 by a sputtering process or the like. Theobtained transparent conductive layer is then subjected tophotolithography and etching, thereby forming the pixel electrodes 9 a.When the electro-optical device is of a reflective type, the pixelelectrodes 9 a may be formed using an opaque material, such as Al,having high reflectance. A polyimide solution to form alignment layersis applied over the pixel electrodes 9 a and then rubbed in apredetermined direction so as to have a predetermined pretilt angle,thereby obtaining the first alignment layer 16.

[0152] On the other hand, with respect to the counter substrate 20, aglass plate or the like is firstly prepared, and a metal layercontaining, for example, chromium is formed on the counter substrate 20by a sputtering process. The metal layer is subjected tophotolithography and etching, thereby forming a light-shielding layerfunctioning as a frame. The light-shielding layer need not be conductiveand may contain a metal, such as Cr, Ni, or Al; resin black havingcarbon or Ti dispersed in a photoresist; or the like.

[0153] Next, a transparent conductive layer, containing ITO or the like,having a thickness of about 50 to 200 nm is formed on the entire surfaceof the counter substrate 20 by a sputtering process or the like, therebyobtaining the counter electrode 21. A polyimide solution to formalignment layers is applied to the entire surface of the counterelectrode 21 and then rubbed in a predetermined direction so as to havea predetermined pretilt angle, thereby obtaining the second alignmentlayer 22.

[0154] Finally, the resulting counter substrate 20 is joined to the TFTarray substrate 10 having the above-mentioned layers thereon with thesealing member 52 such that the second alignment layer 22 faces thefirst alignment layer 16. Liquid crystal, a mixture of a plurality ofnematic liquid crystals is provided in a space between the substrates byvacuum aspiration or the like, thereby obtaining the liquid crystallayer 50 having a predetermined thickness.

[0155] According to the manufacturing steps described above, theelectro-optical device of this exemplary embodiment can be obtained.

[0156] In the above description, the storage capacitors 70 are formed byfirstly forming the lower electrodes 71, and then forming dielectriclayers 75, and capacitor electrodes 300, however, it is possible thatthe second precursor film to form the lower electrodes 71, a sixthprecursor film to form the dielectric layers 75, and the fourthprecursor film to form the capacitor electrodes 300 are formed in thisorder and then etched in one step instead of the above procedure,thereby obtaining the storage capacitors 70.

[0157] Entire Configuration of Electro-Optical Device

[0158] The entire configuration of the electro-optical device accordingto this exemplary embodiment will now be described with reference toFIGS. 8 and 9. FIG. 8 is a plan view showing the TFT array substrate 10having various components thereon when viewed from the counter substrate20 side. FIG. 9 is a sectional view showing taken along the plane H-H′of FIG. 8.

[0159] With reference to FIGS. 8 and 9, the electro-optical device ofthis exemplary embodiment includes the TFT array substrate 10 andcounter substrate 20 facing the TFT array substrate 10. The liquidcrystal layer 50 is disposed between the TFT array substrate 10 andcounter substrate 20 in a sealed manner. The TFT array substrate 10 andcounter substrate 20 are joined to each other with the sealing member 52placed in a sealing region surrounding the image display region 10 a.

[0160] The sealing member 52 contains a UV curable resin, thermosettingresin or the like, and is cured by UV rays, heat or the like when thesubstrates are joined to each other. The sealing member 52 furthercontains gap members (spacers), such as glass fibers or glass beads, forkeeping the distance between the substrates at a predetermined valuewhen the electro-optical device of this exemplary embodiment is used forsmall-sized liquid crystal devices, such as projectors, to display animage in an enlarged manner. Alternatively, such gap members may becontained in the liquid crystal layer 50 when the electro-optical deviceis used for large-sized liquid crystal devices, such as liquid crystaldisplays or liquid crystal TVs, to display an image at 1× magnification.

[0161] In an area outside the sealing member 52, an externalcircuit-connecting terminals 102 and a data line-driving circuit 101 todrive the data lines 6 a by transmitting image signals to the data lines6 a at a predetermined timing are arranged along a side of the TFT arraysubstrate 10. A scanning line-driving circuit 104 to drive the gateelectrodes 3 a by transmitting scanning signals to the scanning lines 11a and the gate electrodes 3 a at a predetermined timing is arrangedalong the two sides adjacent to the above-mentioned side, respectively.

[0162] When a delay in transmitting the scanning signals transmitted tothe scanning lines 11 a and gate electrodes 3 a do not cause anyproblem, it is understood that the scanning line-driving circuit 104 maybe placed along only one side. The data line-driving circuit 101 may beplaced on both sides of the image display region 10 a.

[0163] A plurality of wiring lines 105 to connect the scanningline-driving circuits 104, placed on both sides of the image displayregion 10 a, are arranged along the remaining one side of the TFT arraysubstrate 10.

[0164] A conductive member 106 to electrically connect the TFT arraysubstrate 10 to the counter substrate 20 is placed in at least onecorner of the counter substrate 20.

[0165] With reference to FIG. 9, the TFTs 30 to switch pixels and wiringlines, such as the scanning lines 11 a and the data lines 6 a, arearranged above the TFT array substrate 10. The pixel electrodes 9 a arearranged above the TFTs 30 and wiring lines. The first alignment layer16 is placed above the pixel electrodes 9 a. On the other hand, thecounter electrode 21 and second alignment layer 22, which is theuppermost layer, are placed on the counter substrate 20. The liquidcrystal layer 50 contains a mixture containing one or more kinds ofnematic liquid crystals and takes a predetermined alignment statebetween a pair of the alignment layers 16 and 22. In the liquid crystallayer 50, predetermined alignment is maintained.

[0166] On the TFT array substrate 10, in addition to the dataline-driving circuit 101, scanning line-driving circuits 104 and thelike, there may be provided a sampling circuit to transmit image signalsto a plurality of the data lines 6 a at a predetermined timing, aprecharge circuit to transmit precharge signals having a predeterminedvoltage level to the data lines 6 a prior to the image signals, and aninspection circuit to inspect the quality and/or defects of theelectro-optical device in manufacturing steps and/or at the time ofdelivery, or the like.

[0167] In the above-mentioned exemplary embodiments, instead of placingthe data line-driving circuit 101 and scanning line-driving circuits 104on the TFT array substrate 10, the above components and lines may beelectrically and mechanically connected to, for example, a driving LSImounted on a tape automated bonding (TAB) substrate through ananisotropic conductive film provided in the periphery portion of the TFTarray substrate 10. Furthermore, polarizing films, retardation films,polarizers, or the like are each placed, in a predetermined orientation,on a surface of the counter substrate 20 on which projected light isincident and a surface of the TFT array substrate 10 from which outgoinglight is emitted depending on a display mode, such as a normally whitemode or normally black mode and an operating mode, such as a twistednematic (TN) mode, vertically aligned (VA) mode, or polymer-dispersedliquid crystal (PDLC) mode.

[0168] Electronic Apparatus

[0169] The entire configuration, especially optical configuration of acolor display projector, which is an example in which theelectro-optical device of an aspect of the present invention is used asa light bulb, will now be described. FIG. 10 is a schematic sectionalview showing the color display projector.

[0170]FIG. 10 shows a liquid crystal projector 1100, which is an exampleof a projector type color display device according to this exemplaryembodiment. The liquid crystal projector 1100 includes three liquidcrystal modules, each being used as a red light valve 100R, a greenlight valve 100G, and a blue light valve 100B. These light valves eachinclude a liquid crystal device including a TFT array substrate and adriving circuit mounted thereon. The liquid crystal projector 1100further includes a lamp unit 1102 as a white light source, such as ametal halide lamp; three mirrors 1106; two dichroic mirrors 1108; arelay lens system 1121 including an entrance lens 1122, a relay lens1123, and an emitting lens 1124; a dichroic prism 1112; and a projectinglens 1114. The lamp unit 1102 emits light, which is divided into red,green, and blue light components R, G, and B corresponding to the threeprimary colors. The red, green, and blue light components R, G, and Bare each transmitted to the corresponding red, green, and blue lightvalves 100R, 100G and 100B. In particular, in order to reduce an opticalloss due to long optical path, the blue light component B is guidedthrough the relay lens system 1121. The red, green, and blue lightcomponents R, G and B are each modulated with the corresponding red,green, and blue light valves 100R, 100G and 100B and are then combinedinto one light ray by the dichroic prism 1112. The light ray isprojected onto a screen 1120 through the projecting lens 1114, therebydisplaying a color image.

[0171] The present invention is not limited to the above exemplaryembodiments, and various modifications may be made within the scope andspirit of the present invention specified in the specification andclaims. The present invention is intended to cover modifiedelectro-optical devices, manufacturing process thereof, and electronicapparatus. The electro-optical device of an aspect of the presentinvention can be used for electrophoretic devices, electroluminescent(EL) devices, electron emission element-including devices, such as fieldemission displays and surface-conduction electron-emitter displays.

What is claimed is:
 1. An electro-optical device comprising above asubstrate: data lines extending in a first direction; scanning linesextending in a second direction in such a manner that the scanning linesand data lines intersect each other; pixel electrodes and thin-filmtransistors each placed in regions corresponding to intersections of thescanning lines and data lines; storage capacitors each disposed belowthe data lines and each electrically connected to the correspondingthin-film transistors and pixel electrodes; a capacitor line disposedabove the data lines; first junction electrodes, formed using the samefilm as that used to form the data lines, each electrically connectingthe corresponding pixel potential capacitor electrodes of the storagecapacitors and pixel electrodes; and second junction electrodes, formedusing the same film as that used to form the data lines, eachelectrically connecting the corresponding constant potential capacitorelectrodes and the capacitor line, the data lines, first junctionelectrodes, and second junction electrodes each including a nitridefilm.
 2. The electro-optical device according to claim 1, the datalines, first junction electrodes, and second junction electrodes eachincluding the nitride film on a conductive layer.
 3. The electro-opticaldevice according to claim 2, the data lines, first junction electrodes,and second junction electrodes having laminated layer structureincluding an aluminum film, titanium nitride film, and silicon nitridefilm.
 4. The electro-optical device according to claim 1, furthercomprising: third junction electrodes formed using the same film as thatused to form the capacitor line, the first junction electrodes eachbeing electrically connected to the corresponding pixel electrodes withthe corresponding third junction electrodes.
 5. The electro-opticaldevice according to claim 4, the capacitor line and third junctionelectrodes each including a conductive layer and a nitride film disposedthereon.
 6. The electro-optical device according to claim 5, thecapacitor line and third junction electrodes have laminated layerstructure including an aluminum film, titanium nitride film, and siliconnitride film.
 7. The electro-optical device according to claim 1,further comprising: fourth junction electrodes formed on an insulatinglayer on which the thin-film transistors are formed, the pixel potentialcapacitor electrodes each being electrically connected to thecorresponding first junction electrodes with the corresponding fourthjunction electrodes.
 8. The electro-optical device according to claim 7,the fourth junction electrodes being formed using the same film forforming gate electrodes of the thin-film transistors.
 9. Theelectro-optical device according to claim 1, the scanning lines beingplaced below the thin-film transistors and each being electricallyconnected to the corresponding gate electrodes with contact holes, thegate electrodes being each disposed on corresponding semiconductorlayers each included in the corresponding thin-film transistors.
 10. Theelectro-optical device according to claim 1, the storage capacitors eachincluding corresponding dielectric layers each disposed between thecorresponding pixel potential capacitor electrodes and constantpotential capacitor electrodes, the dielectric layers including aplurality of sub-layers containing different materials, and one of thesub-layers containing a material having a dielectric constant largerthan those of the materials of the other layers.
 11. The electro-opticaldevice according to claim 10, the dielectric layers each includingcorresponding silicon dioxide sub-layers and silicon nitride sub-layers.12. The electro-optical device according to claim 1, the capacitor linebeing made of a light-shielding film and extending along thecorresponding data lines and have a width larger than that of the datalines.
 13. The electro-optical device according to claim 1, furthercomprising: a first insulating layer disposed under the pixel electrodesas the base and a second insulating layer disposed under the capacitorline as the base, at least the surface of the first insulating layerbeing planarized.
 14. An electronic apparatus including anelectro-optical device, the electro-optical device comprising, above asubstrate: data lines extending in a first direction; scanning linesextending in a second direction in such a manner that the scanning linesand data lines intersect each other; pixel electrodes and thin-filmtransistors each placed in corresponding regions corresponding tointersections of the scanning lines and data lines; the storagecapacitors disposed below the data lines and each electrically connectedto the corresponding thin-film transistors and pixel electrodes;capacitor line disposed above the data lines; first junction electrodes,formed using the same film as that used to form the data lines, eachelectrically connecting the corresponding pixel potential capacitorelectrodes and pixel electrodes; and second junction electrodes, formedusing the same film as that used to form the data lines, eachelectrically connecting the corresponding constant potential capacitorelectrodes and the capacitor line, the data lines, first junctionelectrodes, and second junction electrodes each including a nitridefilm.
 15. A method to manufacture an electro-optical device, comprisingforming above a substrate: thin-film transistors; a first interlayerinsulating layer on gate electrodes of the thin-film transistors;storage capacitors each by forming on the first interlayer insulatinglayer, the storage capacitors being each equipped with a pixel potentialcapacitor electrode, dielectric layer, and constant potential capacitorelectrode disposed in order from the bottom; a second interlayerinsulating layer on the storage capacitors; data lines, first junctionelectrodes, and second junction electrodes on the second interlayerinsulating layer using a conductive material containing a nitride film,the data lines being each electrically connected to the correspondingsemiconductor layers of the thin-film transistors, the first junctionelectrodes being each electrically connected to the corresponding pixelpotential capacitor electrodes, and the second junction electrodes beingeach electrically connected to the corresponding constant potentialcapacitor electrodes; a third interlayer insulating layer on the datalines, first junction electrodes, and second junction electrodes; thirdjunction electrodes and a capacitor line on the third interlayerinsulating layer, the third junction electrodes being each electricallyconnected to the corresponding first junction electrodes, and thecapacitor line being electrically connected to the corresponding secondjunction electrodes; a fourth interlayer insulating layer on the thirdjunction electrodes and capacitor line; and pixel electrodes, eachelectrically connected to the corresponding third junction electrodes,on the fourth interlayer insulating layer.
 16. The method according toclaim 15, the forming the storage capacitors including forming a firstprecursor film to form the pixel potential capacitor electrodes; forminga second precursor film to form the dielectric layers on the firstprecursor film; forming a third precursor film to form the constantpotential capacitor electrodes on the second precursor film; and etchingthe first, second, and third precursor films in one step to form thepixel potential capacitor electrodes, dielectric layers, and constantpotential capacitor electrodes.
 17. The method according to claim 15,the forming the storage capacitors including forming a first precursorfilm to form the pixel potential capacitor electrodes; etching the firstprecursor film to form the pixel potential capacitor electrodes; forminga second precursor film to form the dielectric layers on the firstprecursor film; forming a third precursor film to form the constantpotential capacitor electrodes on the second precursor film; and etchingthe third precursor film to form the dielectric layers and constantpotential capacitor electrodes, the constant potential capacitorelectrodes having an area larger than that of the dielectric layers andpixel potential capacitor electrodes.